Microsemi Corporation - Microsemi Libero Software Release v2021.2 (Version 2021.2.0.11)
*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v2021.2 release notes for more details.
Pin Name |
Type |
Net Name |
Cell Name |
Op |
Delay (ns) |
Total (ns) |
Fanout |
Edge |
From: DelayFIFOx128_38_inst/COREFIFO_C1_inst/COREFIFO_C1_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C1_COREFIFO_C1_0_USRAM_top_R0C1/R_DATA_0_inst:CLK |
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To: result_Z[255]:D |
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data required time |
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|
8.211 |
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|
data arrival time |
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|
|
- |
|
6.778 |
|
|
slack |
|
|
|
|
|
1.433 |
|
|
Data arrival time calculation |
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|
clock |
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|
0.000 |
0.000 |
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|
clock |
Clock source |
|
|
+ |
0.000 |
0.000 |
|
r |
BLOCK_INTERFACE_I_clock:A |
net |
I_NET_clock |
|
+ |
0.000 |
0.000 |
|
r |
BLOCK_INTERFACE_I_clock:Y |
cell |
|
ADLIB:CFG1 |
+ |
0.053 |
0.053 |
2 |
r |
I_2/U0_GB0:A |
net |
clock |
|
+ |
0.810 |
0.863 |
|
r |
I_2/U0_GB0:Y |
cell |
|
ADLIB:GB |
+ |
0.128 |
0.991 |
5 |
r |
I_2/U0_RGB1_RGB4:A |
net |
I_2/U0_gbs_1 |
|
+ |
0.341 |
1.332 |
|
r |
I_2/U0_RGB1_RGB4:Y |
cell |
|
ADLIB:RGB |
+ |
0.058 |
1.390 |
2351 |
f |
DelayFIFOx128_38_inst/COREFIFO_C1_inst/COREFIFO_C1_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C1_COREFIFO_C1_0_USRAM_top_R0C1/R_DATA_0_inst:CLK |
net |
I_2/U0_RGB1_RGB4_rgb_net_1 |
|
+ |
0.604 |
1.994 |
|
r |
DelayFIFOx128_38_inst/COREFIFO_C1_inst/COREFIFO_C1_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C1_COREFIFO_C1_0_USRAM_top_R0C1/R_DATA_0_inst:Q |
cell |
|
ADLIB:SLE |
+ |
0.209 |
2.203 |
2 |
r |
un4_result_0_0_cry_12:B |
net |
DelayFIFOx128_38_inst_COREFIFO_C1_inst_COREFIFO_C1_0_RDATA_int[12] |
|
+ |
0.637 |
2.840 |
|
r |
un4_result_0_0_cry_12:P |
cell |
|
ADLIB:ARI1_CC |
+ |
0.094 |
2.934 |
1 |
f |
un4_result_0_0_cry_0_CC_1:P[3] |
net |
NET_CC_CONFIG840 |
|
+ |
0.015 |
2.949 |
|
f |
un4_result_0_0_cry_0_CC_1:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.248 |
3.197 |
1 |
r |
un4_result_0_0_cry_0_CC_2:CI |
net |
CI_TO_CO783 |
|
+ |
0.017 |
3.214 |
|
r |
un4_result_0_0_cry_0_CC_2:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.318 |
1 |
r |
un4_result_0_0_cry_0_CC_3:CI |
net |
CI_TO_CO784 |
|
+ |
0.000 |
3.318 |
|
r |
un4_result_0_0_cry_0_CC_3:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.422 |
1 |
r |
un4_result_0_0_cry_0_CC_4:CI |
net |
CI_TO_CO785 |
|
+ |
0.000 |
3.422 |
|
r |
un4_result_0_0_cry_0_CC_4:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.526 |
1 |
r |
un4_result_0_0_cry_0_CC_5:CI |
net |
CI_TO_CO786 |
|
+ |
0.000 |
3.526 |
|
r |
un4_result_0_0_cry_0_CC_5:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.630 |
1 |
r |
un4_result_0_0_cry_0_CC_6:CI |
net |
CI_TO_CO787 |
|
+ |
0.000 |
3.630 |
|
r |
un4_result_0_0_cry_0_CC_6:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.734 |
1 |
r |
un4_result_0_0_cry_0_CC_7:CI |
net |
CI_TO_CO788 |
|
+ |
0.000 |
3.734 |
|
r |
un4_result_0_0_cry_0_CC_7:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.838 |
1 |
r |
un4_result_0_0_cry_0_CC_8:CI |
net |
CI_TO_CO789 |
|
+ |
0.018 |
3.856 |
|
r |
un4_result_0_0_cry_0_CC_8:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
3.960 |
1 |
r |
un4_result_0_0_cry_0_CC_9:CI |
net |
CI_TO_CO790 |
|
+ |
0.000 |
3.960 |
|
r |
un4_result_0_0_cry_0_CC_9:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
4.064 |
1 |
r |
un4_result_0_0_cry_0_CC_10:CI |
net |
CI_TO_CO791 |
|
+ |
0.000 |
4.064 |
|
r |
un4_result_0_0_cry_0_CC_10:CC[0] |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.055 |
4.119 |
1 |
r |
un4_result_0_0_cry_117:CC |
net |
NET_CC_CONFIG1263 |
|
+ |
0.000 |
4.119 |
|
r |
un4_result_0_0_cry_117:S |
cell |
|
ADLIB:ARI1_CC |
+ |
0.062 |
4.181 |
1 |
r |
un4_result_0_cry_53:A |
net |
un4_result_0_0_Z[117] |
|
+ |
0.801 |
4.982 |
|
r |
un4_result_0_cry_53:P |
cell |
|
ADLIB:ARI1_CC |
+ |
0.051 |
5.033 |
1 |
f |
un4_result_0_cry_0_CC_5:P[2] |
net |
NET_CC_CONFIG226 |
|
+ |
0.017 |
5.050 |
|
f |
un4_result_0_cry_0_CC_5:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.293 |
5.343 |
1 |
f |
un4_result_0_cry_0_CC_6:CI |
net |
CI_TO_CO4 |
|
+ |
0.000 |
5.343 |
|
f |
un4_result_0_cry_0_CC_6:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
5.447 |
1 |
f |
un4_result_0_cry_0_CC_7:CI |
net |
CI_TO_CO5 |
|
+ |
0.000 |
5.447 |
|
f |
un4_result_0_cry_0_CC_7:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
5.551 |
1 |
f |
un4_result_0_cry_0_CC_8:CI |
net |
CI_TO_CO6 |
|
+ |
0.000 |
5.551 |
|
f |
un4_result_0_cry_0_CC_8:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
5.655 |
1 |
f |
un4_result_0_cry_0_CC_9:CI |
net |
CI_TO_CO7 |
|
+ |
0.017 |
5.672 |
|
f |
un4_result_0_cry_0_CC_9:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
5.776 |
1 |
f |
un4_result_0_cry_0_CC_10:CI |
net |
CI_TO_CO8 |
|
+ |
0.000 |
5.776 |
|
f |
un4_result_0_cry_0_CC_10:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
5.880 |
1 |
f |
un4_result_0_cry_0_CC_11:CI |
net |
CI_TO_CO9 |
|
+ |
0.000 |
5.880 |
|
f |
un4_result_0_cry_0_CC_11:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
5.984 |
1 |
f |
un4_result_0_cry_0_CC_12:CI |
net |
CI_TO_CO10 |
|
+ |
0.000 |
5.984 |
|
f |
un4_result_0_cry_0_CC_12:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
6.088 |
1 |
f |
un4_result_0_cry_0_CC_13:CI |
net |
CI_TO_CO11 |
|
+ |
0.000 |
6.088 |
|
f |
un4_result_0_cry_0_CC_13:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
6.192 |
1 |
f |
un4_result_0_cry_0_CC_14:CI |
net |
CI_TO_CO12 |
|
+ |
0.000 |
6.192 |
|
f |
un4_result_0_cry_0_CC_14:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
6.296 |
1 |
f |
un4_result_0_cry_0_CC_15:CI |
net |
CI_TO_CO13 |
|
+ |
0.095 |
6.391 |
|
f |
un4_result_0_cry_0_CC_15:CO |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.104 |
6.495 |
1 |
f |
un4_result_0_cry_0_CC_16:CI |
net |
CI_TO_CO14 |
|
+ |
0.000 |
6.495 |
|
f |
un4_result_0_cry_0_CC_16:CC[8] |
cell |
|
ADLIB:CC_CONFIG |
+ |
0.196 |
6.691 |
1 |
r |
un4_result_0_s_191:CC |
net |
NET_CC_CONFIG781 |
|
+ |
0.000 |
6.691 |
|
r |
un4_result_0_s_191:S |
cell |
|
ADLIB:ARI1_CC |
+ |
0.062 |
6.753 |
1 |
r |
result_Z[255]:D |
net |
un4_result_0_Z[255] |
|
+ |
0.025 |
6.778 |
|
r |
data arrival time |
|
|
|
|
|
6.778 |
|
|
Data required time calculation |
|
|
|
|
|
|
|
|
clock |
Clock Constraint |
|
|
|
6.400 |
6.400 |
|
|
clock |
Clock source |
|
|
+ |
0.000 |
6.400 |
|
r |
BLOCK_INTERFACE_I_clock:A |
net |
I_NET_clock |
|
+ |
0.000 |
6.400 |
|
r |
BLOCK_INTERFACE_I_clock:Y |
cell |
|
ADLIB:CFG1 |
+ |
0.044 |
6.444 |
2 |
r |
I_2/U0_GB0:A |
net |
clock |
|
+ |
0.656 |
7.100 |
|
r |
I_2/U0_GB0:Y |
cell |
|
ADLIB:GB |
+ |
0.117 |
7.217 |
5 |
r |
I_2/U0_RGB1_RGB5:A |
net |
I_2/U0_gbs_1 |
|
+ |
0.298 |
7.515 |
|
r |
I_2/U0_RGB1_RGB5:Y |
cell |
|
ADLIB:RGB |
+ |
0.049 |
7.564 |
54 |
f |
result_Z[255]:CLK |
net |
I_2/U0_RGB1_RGB5_rgb_net_1 |
|
+ |
0.462 |
8.026 |
|
r |
clock reconvergence pessimism |
|
|
|
+ |
0.185 |
8.211 |
|
|
result_Z[255]:D |
Library setup time |
|
ADLIB:SLE |
- |
0.000 |
8.211 |
|
|
data required time |
|
|
|
|
|
8.211 |
|
|
Operating Conditions |
slow_lv_ht |
Pin Name |
Type |
Net Name |
Cell Name |
Op |
Delay (ns) |
Total (ns) |
Fanout |
Edge |
From: resetn |
|
|
|
|
|
|
|
|
To: DelayFIFOx64_19_inst/COREFIFO_C2_inst/COREFIFO_C2_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C2_COREFIFO_C2_0_USRAM_top_R0C5/R_ADDR_2_inst:SLn |
|
|
|
|
|
|
|
|
data required time |
|
|
|
|
|
N/C |
|
|
data arrival time |
|
|
|
- |
|
3.997 |
|
|
slack |
|
|
|
|
|
N/C |
|
|
Data arrival time calculation |
|
|
|
|
|
|
|
|
resetn |
|
|
|
|
0.000 |
0.000 |
|
r |
BLOCK_INTERFACE_I_resetn:A |
net |
I_NET_resetn |
|
+ |
0.000 |
0.000 |
|
r |
BLOCK_INTERFACE_I_resetn:Y |
cell |
|
ADLIB:CFG1 |
+ |
0.053 |
0.053 |
624 |
r |
DelayFIFOx64_19_inst/COREFIFO_C2_inst/COREFIFO_C2_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C2_COREFIFO_C2_0_USRAM_top_R0C5/R_ADDR_2_inst:SLn |
net |
resetn |
|
+ |
3.944 |
3.997 |
|
r |
data arrival time |
|
|
|
|
|
3.997 |
|
|
Data required time calculation |
|
|
|
|
|
|
|
|
clock |
|
|
|
|
N/C |
N/C |
|
|
clock |
Clock source |
|
|
+ |
0.000 |
N/C |
|
r |
BLOCK_INTERFACE_I_clock:A |
net |
I_NET_clock |
|
+ |
0.000 |
N/C |
|
r |
BLOCK_INTERFACE_I_clock:Y |
cell |
|
ADLIB:CFG1 |
+ |
0.044 |
N/C |
2 |
r |
I_2:A |
net |
clock |
|
+ |
0.656 |
N/C |
|
r |
I_2:Y |
cell |
|
ADLIB:GB |
+ |
0.117 |
N/C |
7 |
r |
I_2/U0_RGB1_RGB2:A |
net |
I_2/U0_Y |
|
+ |
0.306 |
N/C |
|
r |
I_2/U0_RGB1_RGB2:Y |
cell |
|
ADLIB:RGB |
+ |
0.049 |
N/C |
2289 |
f |
DelayFIFOx64_19_inst/COREFIFO_C2_inst/COREFIFO_C2_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C2_COREFIFO_C2_0_USRAM_top_R0C5/R_ADDR_2_inst:CLK |
net |
I_2/U0_RGB1_RGB2_rgb_net_1 |
|
+ |
0.494 |
N/C |
|
r |
DelayFIFOx64_19_inst/COREFIFO_C2_inst/COREFIFO_C2_0/genblk24.UI_ram_wrapper_1/U6_syncpipe/COREFIFO_C2_COREFIFO_C2_0_USRAM_top_R0C5/R_ADDR_2_inst:SLn |
Library setup time |
|
ADLIB:SLE |
- |
0.050 |
N/C |
|
|
Operating Conditions |
slow_lv_ht |
Pin Name |
Type |
Net Name |
Cell Name |
Op |
Delay (ns) |
Total (ns) |
Fanout |
Edge |
From: resetn |
|
|
|
|
|
|
|
|
To: mult192x64_inst/mult64x64_prod2/WideMult_2_1/MACC_PHYS_INST/INST_MACC_IP:AL_N |
|
|
|
|
|
|
|
|
data required time |
|
|
|
|
|
N/C |
|
|
data arrival time |
|
|
|
- |
|
2.666 |
|
|
slack |
|
|
|
|
|
N/C |
|
|
Data arrival time calculation |
|
|
|
|
|
|
|
|
resetn |
|
|
|
|
0.000 |
0.000 |
|
r |
BLOCK_INTERFACE_I_resetn:A |
net |
I_NET_resetn |
|
+ |
0.000 |
0.000 |
|
r |
BLOCK_INTERFACE_I_resetn:Y |
cell |
|
ADLIB:CFG1 |
+ |
0.053 |
0.053 |
624 |
r |
I_1:A |
net |
resetn |
|
+ |
1.425 |
1.478 |
|
r |
I_1:Y |
cell |
|
ADLIB:GB |
+ |
0.126 |
1.604 |
7 |
r |
I_1/U0_RGB1_RGB9:A |
net |
I_1/U0_Y |
|
+ |
0.337 |
1.941 |
|
r |
I_1/U0_RGB1_RGB9:Y |
cell |
|
ADLIB:RGB |
+ |
0.058 |
1.999 |
86 |
f |
mult192x64_inst/mult64x64_prod2/WideMult_2_1/MACC_PHYS_INST/INST_MACC_IP:AL_N |
net |
I_1/U0_RGB1_RGB9_rgb_net_1 |
|
+ |
0.667 |
2.666 |
|
r |
data arrival time |
|
|
|
|
|
2.666 |
|
|
Data required time calculation |
|
|
|
|
|
|
|
|
clock |
|
|
|
|
N/C |
N/C |
|
|
clock |
Clock source |
|
|
+ |
0.000 |
N/C |
|
r |
BLOCK_INTERFACE_I_clock:A |
net |
I_NET_clock |
|
+ |
0.000 |
N/C |
|
r |
BLOCK_INTERFACE_I_clock:Y |
cell |
|
ADLIB:CFG1 |
+ |
0.044 |
N/C |
2 |
r |
I_2:A |
net |
clock |
|
+ |
0.656 |
N/C |
|
r |
I_2:Y |
cell |
|
ADLIB:GB |
+ |
0.117 |
N/C |
7 |
r |
I_2/U0_RGB1_RGB9:A |
net |
I_2/U0_Y |
|
+ |
0.299 |
N/C |
|
r |
I_2/U0_RGB1_RGB9:Y |
cell |
|
ADLIB:RGB |
+ |
0.049 |
N/C |
86 |
f |
mult192x64_inst/mult64x64_prod2/WideMult_2_1/MACC_PHYS_INST/INST_MACC_IP:CLK |
net |
I_2/U0_RGB1_RGB9_rgb_net_1 |
|
+ |
0.598 |
N/C |
|
r |
mult192x64_inst/mult64x64_prod2/WideMult_2_1/MACC_PHYS_INST/INST_MACC_IP:AL_N |
Library recovery time |
|
ADLIB:MACC_IP |
- |
0.242 |
N/C |
|
|
Operating Conditions |
slow_lv_ht |