#Build: Synplify Pro (R) R-2021.03M, Build 140R, Jun 17 2021 #install: C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro #OS: Windows 8 6.2 #Hostname: PLA-LT-C32761 # Wed Nov 24 09:50:31 2021 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03M Install: C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro OS: Windows 6.2 Hostname: PLA-LT-C32761 Implementation : synthesis Synopsys HDL Compiler, Version comp202103synp1, Build 142R, Built Jun 17 2021 10:57:57, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03M Install: C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro OS: Windows 6.2 Hostname: PLA-LT-C32761 Implementation : synthesis Synopsys Verilog Compiler, Version comp202103synp1, Build 142R, Built Jun 17 2021 10:57:57, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro\lib\generic\acg5.v" (library work) @I::"C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\actelprj\RTL\WideMult\WideMult\component\polarfire_syn_comps.v" (library work) @W:CG100 : polarfire_syn_comps.v(21) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(61) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(88) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(120) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(172) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(219) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(238) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(287) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(341) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(663) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(767) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(803) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1067) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1377) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1406) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1453) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1486) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1504) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1530) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1571) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1593) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1611) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1628) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1647) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1664) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1693) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1724) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(1814) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2038) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2199) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2215) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2231) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2247) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2279) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(2660) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3673) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3744) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3873) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3891) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3908) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3923) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3938) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(3965) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4076) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4108) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4156) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4266) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4450) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4491) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4519) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4538) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(4617) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(5381) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6191) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6300) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6338) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(6411) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(7300) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(8357) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(9316) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10052) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10767) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10801) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10837) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10884) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(10918) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(11784) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12827) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12843) | User defined pragma syn_black_box detected @W:CG100 : polarfire_syn_comps.v(12856) | User defined pragma syn_black_box detected @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_sync_scntr.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\COREFIFO_C3_COREFIFO_C3_0_USRAM_top.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_NstagesSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_grayToBinConv.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_async.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_fwft.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_resetSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_sync.v" (library work) @W:CG1337 : corefifo_sync.v(300) | Net almostfulli_deassert is not declared. @W:CG1337 : corefifo_sync.v(305) | Net almostemptyi_deassert is not declared. @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\COREFIFO.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\DelayFIFOx128_18.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_sync_scntr.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\COREFIFO_C1_COREFIFO_C1_0_USRAM_top.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_NstagesSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_grayToBinConv.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_async.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_fwft.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_resetSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_sync.v" (library work) @W:CG1337 : corefifo_sync.v(300) | Net almostfulli_deassert is not declared. @W:CG1337 : corefifo_sync.v(305) | Net almostemptyi_deassert is not declared. @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\COREFIFO.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\DelayFIFOx128_38.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_sync_scntr.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\COREFIFO_C2_COREFIFO_C2_0_USRAM_top.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_NstagesSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_grayToBinConv.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_async.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_fwft.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_resetSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_sync.v" (library work) @W:CG1337 : corefifo_sync.v(300) | Net almostfulli_deassert is not declared. @W:CG1337 : corefifo_sync.v(305) | Net almostemptyi_deassert is not declared. @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\COREFIFO.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\DelayFIFOx64_19.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_USRAM_top.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_NstagesSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_grayToBinConv.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_resetSync.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v" (library work) @W:CG1337 : corefifo_sync.v(300) | Net almostfulli_deassert is not declared. @W:CG1337 : corefifo_sync.v(305) | Net almostemptyi_deassert is not declared. @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\DelayFIFOx64_38.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\mult64x64.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\mult128x64.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\mult192x64.v" (library work) @I::"C:\actelprj\RTL\WideMult\WideMult\hdl\WideMultTopPF.v" (library work) Verilog syntax check successful! File C:\actelprj\RTL\WideMult\WideMult\component\polarfire_syn_comps.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_NstagesSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_grayToBinConv.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_async.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_fwft.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_resetSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_sync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\corefifo_sync_scntr.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\COREFIFO_C3_COREFIFO_C3_0_USRAM_top.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3_0\rtl\vlog\core\COREFIFO.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C3\COREFIFO_C3.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_NstagesSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_grayToBinConv.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_async.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_fwft.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_resetSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_sync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\corefifo_sync_scntr.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\COREFIFO_C1_COREFIFO_C1_0_USRAM_top.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1_0\rtl\vlog\core\COREFIFO.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C1\COREFIFO_C1.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_NstagesSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_grayToBinConv.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_async.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_fwft.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_resetSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_sync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\corefifo_sync_scntr.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\COREFIFO_C2_COREFIFO_C2_0_USRAM_top.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2_0\rtl\vlog\core\COREFIFO.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C2\COREFIFO_C2.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_NstagesSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_grayToBinConv.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_resetSync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_USRAM_top.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v changed - recompiling File C:\actelprj\RTL\WideMult\WideMult\component\work\COREFIFO_C0\COREFIFO_C0.v changed - recompiling Selecting top level module WideMultTop @N:CG364 : mult64x64.v(28) | Synthesizing module mult64x64 in library work. WIDTH1=32'b00000000000000000000000001000000 WIDTH2=32'b00000000000000000000000001000001 Generated name = mult64x64_64s_65s Running optimization stage 1 on mult64x64_64s_65s ....... Finished optimization stage 1 on mult64x64_64s_65s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 107MB) @N:CG364 : mult64x64.v(28) | Synthesizing module mult64x64 in library work. WIDTH1=32'b00000000000000000000000001000000 WIDTH2=32'b00000000000000000000000001000000 Generated name = mult64x64_64s_64s Running optimization stage 1 on mult64x64_64s_64s ....... Finished optimization stage 1 on mult64x64_64s_64s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 107MB) @N:CG364 : mult128x64.v(48) | Synthesizing module mult128x64 in library work. Running optimization stage 1 on mult128x64 ....... Finished optimization stage 1 on mult128x64 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 107MB) @N:CG364 : mult192x64.v(58) | Synthesizing module mult192x64 in library work. Running optimization stage 1 on mult192x64 ....... Finished optimization stage 1 on mult192x64 (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 107MB) @N:CG364 : COREFIFO.v(29) | Synthesizing module COREFIFO_C3_COREFIFO_C3_0_COREFIFO in library work. FAMILY=32'b00000000000000000000000000011010 SYNC=32'b00000000000000000000000000000001 RCLK_EDGE=32'b00000000000000000000000000000001 WCLK_EDGE=32'b00000000000000000000000000000001 RE_POLARITY=32'b00000000000000000000000000000000 WE_POLARITY=32'b00000000000000000000000000000000 RWIDTH=32'b00000000000000000000000010000000 WWIDTH=32'b00000000000000000000000010000000 RDEPTH=32'b00000000000000000000000001000000 WDEPTH=32'b00000000000000000000000001000000 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 CTRL_TYPE=32'b00000000000000000000000000000011 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 AE_STATIC_EN=32'b00000000000000000000000000000000 AF_STATIC_EN=32'b00000000000000000000000000000001 AEVAL=32'b00000000000000000000000000000100 AFVAL=32'b00000000000000000000000000001110 PIPE=32'b00000000000000000000000000000010 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 RESET_POLARITY=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 NUM_STAGES=32'b00000000000000000000000000000010 WMSB_DEPTH=32'b00000000000000000000000000000110 RMSB_DEPTH=32'b00000000000000000000000000000110 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C3_COREFIFO_C3_0_COREFIFO_Z1 @W:CG168 : COREFIFO.v(517) | Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : corefifo_sync_scntr.v(28) | Synthesizing module COREFIFO_C3_COREFIFO_C3_0_corefifo_sync_scntr in library work. WRITE_WIDTH=32'b00000000000000000000000010000000 WRITE_DEPTH=32'b00000000000000000000000000000110 FULL_WRITE_DEPTH=32'b00000000000000000000000001000000 READ_WIDTH=32'b00000000000000000000000010000000 READ_DEPTH=32'b00000000000000000000000000000110 FULL_READ_DEPTH=32'b00000000000000000000000001000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 WCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 AF_FLAG_STATIC=32'b00000000000000000000000000000001 AE_FLAG_STATIC=32'b00000000000000000000000000000000 AFULL_VAL=32'b00000000000000000000000000001110 AEMPTY_VAL=32'b00000000000000000000000000000100 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 REGISTER_RADDR=32'b00000000000000000000000000000010 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C3_COREFIFO_C3_0_corefifo_sync_scntr_Z2 @W:CG360 : corefifo_sync_scntr.v(160) | Removing wire almostfulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(161) | Removing wire almostfulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(162) | Removing wire fulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(163) | Removing wire fulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(171) | Removing wire neg_reset, as there is no assignment to it. @W:CG184 : corefifo_sync_scntr.v(172) | Removing wire re_top_p, as it has the load but no drivers. Running optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_corefifo_sync_scntr_Z2 ....... @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register empty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register full_reg. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register empty_top_fwft_r. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(336) | Pruning unused register sc_r_fwft[6:0]. Make sure that there are no unused intermediate registers. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.wack_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.overflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to underflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to dvld_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(260) | All reachable assignments to rdcnt[6:0] assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(240) | All reachable assignments to wrcnt[6:0] assign 0, register removed by optimization. @W:CL190 : corefifo_sync_scntr.v(411) | Optimizing register bit dvld_r2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_corefifo_sync_scntr_Z2 (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @N:CG364 : acg5.v(508) | Synthesizing module RAM64x12 in library work. Running optimization stage 1 on RAM64x12 ....... Finished optimization stage 1 on RAM64x12 (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @N:CG364 : acg5.v(500) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @N:CG364 : acg5.v(504) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @N:CG364 : COREFIFO_C3_COREFIFO_C3_0_USRAM_top.v(5) | Synthesizing module COREFIFO_C3_COREFIFO_C3_0_USRAM_top in library work. Running optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_USRAM_top ....... Finished optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @N:CG364 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(4) | Synthesizing module COREFIFO_C3_COREFIFO_C3_0_ram_wrapper in library work. RWIDTH=32'b00000000000000000000000010000000 WWIDTH=32'b00000000000000000000000010000000 RDEPTH=32'b00000000000000000000000000000110 WDEPTH=32'b00000000000000000000000000000110 SYNC=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 CTRL_TYPE=32'b00000000000000000000000000000011 Generated name = COREFIFO_C3_COREFIFO_C3_0_ram_wrapper_128s_128s_6_6_1s_2s_3s Running optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_ram_wrapper_128s_128s_6_6_1s_2s_3s ....... @W:CL318 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(44) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(45) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(46) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(47) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_ram_wrapper_128s_128s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @W:CG360 : COREFIFO.v(165) | Removing wire SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(166) | Removing wire DB_DETECT, as there is no assignment to it. @W:CG184 : COREFIFO.v(197) | Removing wire EMPTY2, as it has the load but no drivers. @W:CG360 : COREFIFO.v(198) | Removing wire AEMPTY2, as there is no assignment to it. @W:CG360 : COREFIFO.v(199) | Removing wire fifo_rd_en, as there is no assignment to it. @W:CG360 : COREFIFO.v(203) | Removing wire pf_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(204) | Removing wire fwft_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(209) | Removing wire pf_Q, as there is no assignment to it. @W:CG360 : COREFIFO.v(210) | Removing wire fwft_Q, as there is no assignment to it. @W:CG184 : COREFIFO.v(228) | Removing wire DVLD_async, as it has the load but no drivers. @W:CG184 : COREFIFO.v(230) | Removing wire DVLD_sync, as it has the load but no drivers. @W:CG360 : COREFIFO.v(231) | Removing wire fwft_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(232) | Removing wire fwft_reg_valid, as there is no assignment to it. @W:CG360 : COREFIFO.v(233) | Removing wire pf_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(238) | Removing wire A_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(239) | Removing wire A_DB_DETECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(240) | Removing wire B_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(241) | Removing wire B_DB_DETECT, as there is no assignment to it. @W:CG133 : COREFIFO.v(242) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : COREFIFO.v(256) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : COREFIFO.v(274) | Removing wire reset_sync_r, as there is no assignment to it. @W:CG360 : COREFIFO.v(275) | Removing wire reset_sync_w, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_COREFIFO_Z1 ....... @W:CL318 : COREFIFO.v(165) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO.v(166) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : COREFIFO.v(1060) | Pruning unused register RDATA_ext_r1[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1050) | Pruning unused register RDATA_ext_r[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register REN_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register RE_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(973) | Pruning unused register RDATA_r2[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(953) | Pruning unused register RDATA_r_pre[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(943) | Pruning unused register fwft_Q_r[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(930) | Pruning unused register RDATA_r[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C3_COREFIFO_C3_0_COREFIFO_Z1 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 108MB) @N:CG364 : COREFIFO_C3.v(49) | Synthesizing module COREFIFO_C3 in library work. Running optimization stage 1 on COREFIFO_C3 ....... Finished optimization stage 1 on COREFIFO_C3 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 108MB) @N:CG364 : DelayFIFOx128_18.v(21) | Synthesizing module DelayFIFOx128_18 in library work. Running optimization stage 1 on DelayFIFOx128_18 ....... Finished optimization stage 1 on DelayFIFOx128_18 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 108MB) @N:CG364 : COREFIFO.v(29) | Synthesizing module COREFIFO_C2_COREFIFO_C2_0_COREFIFO in library work. FAMILY=32'b00000000000000000000000000011010 SYNC=32'b00000000000000000000000000000001 RCLK_EDGE=32'b00000000000000000000000000000001 WCLK_EDGE=32'b00000000000000000000000000000001 RE_POLARITY=32'b00000000000000000000000000000000 WE_POLARITY=32'b00000000000000000000000000000000 RWIDTH=32'b00000000000000000000000001000000 WWIDTH=32'b00000000000000000000000001000000 RDEPTH=32'b00000000000000000000000001000000 WDEPTH=32'b00000000000000000000000001000000 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 CTRL_TYPE=32'b00000000000000000000000000000011 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 AE_STATIC_EN=32'b00000000000000000000000000000000 AF_STATIC_EN=32'b00000000000000000000000000000001 AEVAL=32'b00000000000000000000000000000100 AFVAL=32'b00000000000000000000000000001111 PIPE=32'b00000000000000000000000000000010 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 RESET_POLARITY=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 NUM_STAGES=32'b00000000000000000000000000000010 WMSB_DEPTH=32'b00000000000000000000000000000110 RMSB_DEPTH=32'b00000000000000000000000000000110 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C2_COREFIFO_C2_0_COREFIFO_Z3 @W:CG168 : COREFIFO.v(517) | Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : corefifo_sync_scntr.v(28) | Synthesizing module COREFIFO_C2_COREFIFO_C2_0_corefifo_sync_scntr in library work. WRITE_WIDTH=32'b00000000000000000000000001000000 WRITE_DEPTH=32'b00000000000000000000000000000110 FULL_WRITE_DEPTH=32'b00000000000000000000000001000000 READ_WIDTH=32'b00000000000000000000000001000000 READ_DEPTH=32'b00000000000000000000000000000110 FULL_READ_DEPTH=32'b00000000000000000000000001000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 WCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 AF_FLAG_STATIC=32'b00000000000000000000000000000001 AE_FLAG_STATIC=32'b00000000000000000000000000000000 AFULL_VAL=32'b00000000000000000000000000001111 AEMPTY_VAL=32'b00000000000000000000000000000100 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 REGISTER_RADDR=32'b00000000000000000000000000000010 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C2_COREFIFO_C2_0_corefifo_sync_scntr_Z4 @W:CG360 : corefifo_sync_scntr.v(160) | Removing wire almostfulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(161) | Removing wire almostfulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(162) | Removing wire fulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(163) | Removing wire fulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(171) | Removing wire neg_reset, as there is no assignment to it. @W:CG184 : corefifo_sync_scntr.v(172) | Removing wire re_top_p, as it has the load but no drivers. Running optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_corefifo_sync_scntr_Z4 ....... @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register empty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register full_reg. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register empty_top_fwft_r. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(336) | Pruning unused register sc_r_fwft[6:0]. Make sure that there are no unused intermediate registers. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.wack_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.overflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to underflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to dvld_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(260) | All reachable assignments to rdcnt[6:0] assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(240) | All reachable assignments to wrcnt[6:0] assign 0, register removed by optimization. @W:CL190 : corefifo_sync_scntr.v(411) | Optimizing register bit dvld_r2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_corefifo_sync_scntr_Z4 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : COREFIFO_C2_COREFIFO_C2_0_USRAM_top.v(5) | Synthesizing module COREFIFO_C2_COREFIFO_C2_0_USRAM_top in library work. Running optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_USRAM_top ....... Finished optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(4) | Synthesizing module COREFIFO_C2_COREFIFO_C2_0_ram_wrapper in library work. RWIDTH=32'b00000000000000000000000001000000 WWIDTH=32'b00000000000000000000000001000000 RDEPTH=32'b00000000000000000000000000000110 WDEPTH=32'b00000000000000000000000000000110 SYNC=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 CTRL_TYPE=32'b00000000000000000000000000000011 Generated name = COREFIFO_C2_COREFIFO_C2_0_ram_wrapper_64s_64s_6_6_1s_2s_3s Running optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_ram_wrapper_64s_64s_6_6_1s_2s_3s ....... @W:CL318 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(44) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(45) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(46) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(47) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_ram_wrapper_64s_64s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @W:CG360 : COREFIFO.v(165) | Removing wire SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(166) | Removing wire DB_DETECT, as there is no assignment to it. @W:CG184 : COREFIFO.v(197) | Removing wire EMPTY2, as it has the load but no drivers. @W:CG360 : COREFIFO.v(198) | Removing wire AEMPTY2, as there is no assignment to it. @W:CG360 : COREFIFO.v(199) | Removing wire fifo_rd_en, as there is no assignment to it. @W:CG360 : COREFIFO.v(203) | Removing wire pf_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(204) | Removing wire fwft_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(209) | Removing wire pf_Q, as there is no assignment to it. @W:CG360 : COREFIFO.v(210) | Removing wire fwft_Q, as there is no assignment to it. @W:CG184 : COREFIFO.v(228) | Removing wire DVLD_async, as it has the load but no drivers. @W:CG184 : COREFIFO.v(230) | Removing wire DVLD_sync, as it has the load but no drivers. @W:CG360 : COREFIFO.v(231) | Removing wire fwft_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(232) | Removing wire fwft_reg_valid, as there is no assignment to it. @W:CG360 : COREFIFO.v(233) | Removing wire pf_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(238) | Removing wire A_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(239) | Removing wire A_DB_DETECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(240) | Removing wire B_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(241) | Removing wire B_DB_DETECT, as there is no assignment to it. @W:CG133 : COREFIFO.v(242) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : COREFIFO.v(256) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : COREFIFO.v(274) | Removing wire reset_sync_r, as there is no assignment to it. @W:CG360 : COREFIFO.v(275) | Removing wire reset_sync_w, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_COREFIFO_Z3 ....... @W:CL318 : COREFIFO.v(165) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO.v(166) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : COREFIFO.v(1060) | Pruning unused register RDATA_ext_r1[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1050) | Pruning unused register RDATA_ext_r[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register REN_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register RE_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(973) | Pruning unused register RDATA_r2[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(953) | Pruning unused register RDATA_r_pre[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(943) | Pruning unused register fwft_Q_r[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(930) | Pruning unused register RDATA_r[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C2_COREFIFO_C2_0_COREFIFO_Z3 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : COREFIFO_C2.v(49) | Synthesizing module COREFIFO_C2 in library work. Running optimization stage 1 on COREFIFO_C2 ....... Finished optimization stage 1 on COREFIFO_C2 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : DelayFIFOx64_19.v(21) | Synthesizing module DelayFIFOx64_19 in library work. Running optimization stage 1 on DelayFIFOx64_19 ....... Finished optimization stage 1 on DelayFIFOx64_19 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : COREFIFO.v(29) | Synthesizing module COREFIFO_C1_COREFIFO_C1_0_COREFIFO in library work. FAMILY=32'b00000000000000000000000000011010 SYNC=32'b00000000000000000000000000000001 RCLK_EDGE=32'b00000000000000000000000000000001 WCLK_EDGE=32'b00000000000000000000000000000001 RE_POLARITY=32'b00000000000000000000000000000000 WE_POLARITY=32'b00000000000000000000000000000000 RWIDTH=32'b00000000000000000000000010000000 WWIDTH=32'b00000000000000000000000010000000 RDEPTH=32'b00000000000000000000000001000000 WDEPTH=32'b00000000000000000000000001000000 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 CTRL_TYPE=32'b00000000000000000000000000000011 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 AE_STATIC_EN=32'b00000000000000000000000000000000 AF_STATIC_EN=32'b00000000000000000000000000000001 AEVAL=32'b00000000000000000000000000000100 AFVAL=32'b00000000000000000000000000100001 PIPE=32'b00000000000000000000000000000010 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 RESET_POLARITY=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 NUM_STAGES=32'b00000000000000000000000000000010 WMSB_DEPTH=32'b00000000000000000000000000000110 RMSB_DEPTH=32'b00000000000000000000000000000110 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C1_COREFIFO_C1_0_COREFIFO_Z5 @W:CG168 : COREFIFO.v(517) | Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : corefifo_sync_scntr.v(28) | Synthesizing module COREFIFO_C1_COREFIFO_C1_0_corefifo_sync_scntr in library work. WRITE_WIDTH=32'b00000000000000000000000010000000 WRITE_DEPTH=32'b00000000000000000000000000000110 FULL_WRITE_DEPTH=32'b00000000000000000000000001000000 READ_WIDTH=32'b00000000000000000000000010000000 READ_DEPTH=32'b00000000000000000000000000000110 FULL_READ_DEPTH=32'b00000000000000000000000001000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 WCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 AF_FLAG_STATIC=32'b00000000000000000000000000000001 AE_FLAG_STATIC=32'b00000000000000000000000000000000 AFULL_VAL=32'b00000000000000000000000000100001 AEMPTY_VAL=32'b00000000000000000000000000000100 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 REGISTER_RADDR=32'b00000000000000000000000000000010 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C1_COREFIFO_C1_0_corefifo_sync_scntr_Z6 @W:CG360 : corefifo_sync_scntr.v(160) | Removing wire almostfulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(161) | Removing wire almostfulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(162) | Removing wire fulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(163) | Removing wire fulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(171) | Removing wire neg_reset, as there is no assignment to it. @W:CG184 : corefifo_sync_scntr.v(172) | Removing wire re_top_p, as it has the load but no drivers. Running optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_corefifo_sync_scntr_Z6 ....... @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register empty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register full_reg. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register empty_top_fwft_r. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(336) | Pruning unused register sc_r_fwft[6:0]. Make sure that there are no unused intermediate registers. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.wack_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.overflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to underflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to dvld_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(260) | All reachable assignments to rdcnt[6:0] assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(240) | All reachable assignments to wrcnt[6:0] assign 0, register removed by optimization. @W:CL190 : corefifo_sync_scntr.v(411) | Optimizing register bit dvld_r2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_corefifo_sync_scntr_Z6 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : COREFIFO_C1_COREFIFO_C1_0_USRAM_top.v(5) | Synthesizing module COREFIFO_C1_COREFIFO_C1_0_USRAM_top in library work. Running optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_USRAM_top ....... Finished optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(4) | Synthesizing module COREFIFO_C1_COREFIFO_C1_0_ram_wrapper in library work. RWIDTH=32'b00000000000000000000000010000000 WWIDTH=32'b00000000000000000000000010000000 RDEPTH=32'b00000000000000000000000000000110 WDEPTH=32'b00000000000000000000000000000110 SYNC=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 CTRL_TYPE=32'b00000000000000000000000000000011 Generated name = COREFIFO_C1_COREFIFO_C1_0_ram_wrapper_128s_128s_6_6_1s_2s_3s Running optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_ram_wrapper_128s_128s_6_6_1s_2s_3s ....... @W:CL318 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(44) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(45) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(46) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(47) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_ram_wrapper_128s_128s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @W:CG360 : COREFIFO.v(165) | Removing wire SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(166) | Removing wire DB_DETECT, as there is no assignment to it. @W:CG184 : COREFIFO.v(197) | Removing wire EMPTY2, as it has the load but no drivers. @W:CG360 : COREFIFO.v(198) | Removing wire AEMPTY2, as there is no assignment to it. @W:CG360 : COREFIFO.v(199) | Removing wire fifo_rd_en, as there is no assignment to it. @W:CG360 : COREFIFO.v(203) | Removing wire pf_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(204) | Removing wire fwft_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(209) | Removing wire pf_Q, as there is no assignment to it. @W:CG360 : COREFIFO.v(210) | Removing wire fwft_Q, as there is no assignment to it. @W:CG184 : COREFIFO.v(228) | Removing wire DVLD_async, as it has the load but no drivers. @W:CG184 : COREFIFO.v(230) | Removing wire DVLD_sync, as it has the load but no drivers. @W:CG360 : COREFIFO.v(231) | Removing wire fwft_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(232) | Removing wire fwft_reg_valid, as there is no assignment to it. @W:CG360 : COREFIFO.v(233) | Removing wire pf_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(238) | Removing wire A_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(239) | Removing wire A_DB_DETECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(240) | Removing wire B_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(241) | Removing wire B_DB_DETECT, as there is no assignment to it. @W:CG133 : COREFIFO.v(242) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : COREFIFO.v(256) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : COREFIFO.v(274) | Removing wire reset_sync_r, as there is no assignment to it. @W:CG360 : COREFIFO.v(275) | Removing wire reset_sync_w, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_COREFIFO_Z5 ....... @W:CL318 : COREFIFO.v(165) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO.v(166) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : COREFIFO.v(1060) | Pruning unused register RDATA_ext_r1[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1050) | Pruning unused register RDATA_ext_r[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register REN_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register RE_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(973) | Pruning unused register RDATA_r2[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(953) | Pruning unused register RDATA_r_pre[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(943) | Pruning unused register fwft_Q_r[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(930) | Pruning unused register RDATA_r[127:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C1_COREFIFO_C1_0_COREFIFO_Z5 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : COREFIFO_C1.v(49) | Synthesizing module COREFIFO_C1 in library work. Running optimization stage 1 on COREFIFO_C1 ....... Finished optimization stage 1 on COREFIFO_C1 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : DelayFIFOx128_38.v(21) | Synthesizing module DelayFIFOx128_38 in library work. Running optimization stage 1 on DelayFIFOx128_38 ....... Finished optimization stage 1 on DelayFIFOx128_38 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : COREFIFO.v(29) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_COREFIFO in library work. FAMILY=32'b00000000000000000000000000011010 SYNC=32'b00000000000000000000000000000001 RCLK_EDGE=32'b00000000000000000000000000000001 WCLK_EDGE=32'b00000000000000000000000000000001 RE_POLARITY=32'b00000000000000000000000000000000 WE_POLARITY=32'b00000000000000000000000000000000 RWIDTH=32'b00000000000000000000000001000000 WWIDTH=32'b00000000000000000000000001000000 RDEPTH=32'b00000000000000000000000001000000 WDEPTH=32'b00000000000000000000000001000000 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 CTRL_TYPE=32'b00000000000000000000000000000011 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 AE_STATIC_EN=32'b00000000000000000000000000000000 AF_STATIC_EN=32'b00000000000000000000000000000001 AEVAL=32'b00000000000000000000000000000100 AFVAL=32'b00000000000000000000000000100001 PIPE=32'b00000000000000000000000000000010 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 RESET_POLARITY=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 NUM_STAGES=32'b00000000000000000000000000000010 WMSB_DEPTH=32'b00000000000000000000000000000110 RMSB_DEPTH=32'b00000000000000000000000000000110 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z7 @W:CG168 : COREFIFO.v(517) | Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : corefifo_sync_scntr.v(28) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr in library work. WRITE_WIDTH=32'b00000000000000000000000001000000 WRITE_DEPTH=32'b00000000000000000000000000000110 FULL_WRITE_DEPTH=32'b00000000000000000000000001000000 READ_WIDTH=32'b00000000000000000000000001000000 READ_DEPTH=32'b00000000000000000000000000000110 FULL_READ_DEPTH=32'b00000000000000000000000001000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000000 WCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 AF_FLAG_STATIC=32'b00000000000000000000000000000001 AE_FLAG_STATIC=32'b00000000000000000000000000000000 AFULL_VAL=32'b00000000000000000000000000100001 AEMPTY_VAL=32'b00000000000000000000000000000100 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 REGISTER_RADDR=32'b00000000000000000000000000000010 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 WDEPTH_CAL=32'b00000000000000000000000000000101 RDEPTH_CAL=32'b00000000000000000000000000000101 Generated name = COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z8 @W:CG360 : corefifo_sync_scntr.v(160) | Removing wire almostfulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(161) | Removing wire almostfulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(162) | Removing wire fulli_assert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(163) | Removing wire fulli_deassert, as there is no assignment to it. @W:CG360 : corefifo_sync_scntr.v(171) | Removing wire neg_reset, as there is no assignment to it. @W:CG184 : corefifo_sync_scntr.v(172) | Removing wire re_top_p, as it has the load but no drivers. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z8 ....... @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register empty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(433) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register full_reg. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register empty_top_fwft_r. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(336) | Pruning unused register sc_r_fwft[6:0]. Make sure that there are no unused intermediate registers. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.wack_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(486) | All reachable assignments to genblk6.overflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to underflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(433) | All reachable assignments to dvld_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(260) | All reachable assignments to rdcnt[6:0] assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(240) | All reachable assignments to wrcnt[6:0] assign 0, register removed by optimization. @W:CL190 : corefifo_sync_scntr.v(411) | Optimizing register bit dvld_r2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : corefifo_sync_scntr.v(411) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z8 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) @N:CG364 : COREFIFO_C0_COREFIFO_C0_0_USRAM_top.v(5) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_USRAM_top in library work. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_USRAM_top ....... Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) @N:CG364 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(4) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper in library work. RWIDTH=32'b00000000000000000000000001000000 WWIDTH=32'b00000000000000000000000001000000 RDEPTH=32'b00000000000000000000000000000110 WDEPTH=32'b00000000000000000000000000000110 SYNC=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000010 CTRL_TYPE=32'b00000000000000000000000000000011 Generated name = COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_64s_64s_6_6_1s_2s_3s Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_64s_64s_6_6_1s_2s_3s ....... @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(44) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(45) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(46) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(47) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_64s_64s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) @W:CG360 : COREFIFO.v(165) | Removing wire SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(166) | Removing wire DB_DETECT, as there is no assignment to it. @W:CG184 : COREFIFO.v(197) | Removing wire EMPTY2, as it has the load but no drivers. @W:CG360 : COREFIFO.v(198) | Removing wire AEMPTY2, as there is no assignment to it. @W:CG360 : COREFIFO.v(199) | Removing wire fifo_rd_en, as there is no assignment to it. @W:CG360 : COREFIFO.v(203) | Removing wire pf_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(204) | Removing wire fwft_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(209) | Removing wire pf_Q, as there is no assignment to it. @W:CG360 : COREFIFO.v(210) | Removing wire fwft_Q, as there is no assignment to it. @W:CG184 : COREFIFO.v(228) | Removing wire DVLD_async, as it has the load but no drivers. @W:CG184 : COREFIFO.v(230) | Removing wire DVLD_sync, as it has the load but no drivers. @W:CG360 : COREFIFO.v(231) | Removing wire fwft_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(232) | Removing wire fwft_reg_valid, as there is no assignment to it. @W:CG360 : COREFIFO.v(233) | Removing wire pf_dvld, as there is no assignment to it. @W:CG360 : COREFIFO.v(238) | Removing wire A_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(239) | Removing wire A_DB_DETECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(240) | Removing wire B_SB_CORRECT, as there is no assignment to it. @W:CG360 : COREFIFO.v(241) | Removing wire B_DB_DETECT, as there is no assignment to it. @W:CG133 : COREFIFO.v(242) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : COREFIFO.v(256) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : COREFIFO.v(274) | Removing wire reset_sync_r, as there is no assignment to it. @W:CG360 : COREFIFO.v(275) | Removing wire reset_sync_w, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z7 ....... @W:CL318 : COREFIFO.v(165) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO.v(166) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : COREFIFO.v(1060) | Pruning unused register RDATA_ext_r1[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1050) | Pruning unused register RDATA_ext_r[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register REN_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register RE_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(985) | Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(973) | Pruning unused register RDATA_r2[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(953) | Pruning unused register RDATA_r_pre[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(943) | Pruning unused register fwft_Q_r[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(930) | Pruning unused register RDATA_r[63:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(418) | Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(405) | Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z7 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) @N:CG364 : COREFIFO_C0.v(49) | Synthesizing module COREFIFO_C0 in library work. Running optimization stage 1 on COREFIFO_C0 ....... Finished optimization stage 1 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) @N:CG364 : DelayFIFOx64_38.v(21) | Synthesizing module DelayFIFOx64_38 in library work. Running optimization stage 1 on DelayFIFOx64_38 ....... Finished optimization stage 1 on DelayFIFOx64_38 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) @N:CG364 : WideMultTopPF.v(52) | Synthesizing module WideMultTop in library work. Running optimization stage 1 on WideMultTop ....... Finished optimization stage 1 on WideMultTop (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB) Running optimization stage 2 on WideMultTop ....... Finished optimization stage 2 on WideMultTop (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on DelayFIFOx64_38 ....... Finished optimization stage 2 on DelayFIFOx64_38 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on COREFIFO_C0 ....... Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_64s_64s_6_6_1s_2s_3s ....... @N:CL159 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(42) | Input WCLOCK is unused. @N:CL159 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(43) | Input RCLOCK is unused. Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_64s_64s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_USRAM_top ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z8 ....... @N:CL159 : corefifo_sync_scntr.v(97) | Input re_top is unused. @N:CL159 : corefifo_sync_scntr.v(98) | Input empty_top_fwft is unused. Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z8 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z7 ....... @W:CL156 : COREFIFO.v(197) | *Input EMPTY2 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : COREFIFO.v(163) | Input MEMRD is unused. Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z7 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on DelayFIFOx128_38 ....... Finished optimization stage 2 on DelayFIFOx128_38 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C1 ....... Finished optimization stage 2 on COREFIFO_C1 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_ram_wrapper_128s_128s_6_6_1s_2s_3s ....... @N:CL159 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(42) | Input WCLOCK is unused. @N:CL159 : COREFIFO_C1_COREFIFO_C1_0_ram_wrapper.v(43) | Input RCLOCK is unused. Finished optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_ram_wrapper_128s_128s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_USRAM_top ....... Finished optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_corefifo_sync_scntr_Z6 ....... @N:CL159 : corefifo_sync_scntr.v(97) | Input re_top is unused. @N:CL159 : corefifo_sync_scntr.v(98) | Input empty_top_fwft is unused. Finished optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_corefifo_sync_scntr_Z6 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_COREFIFO_Z5 ....... @W:CL156 : COREFIFO.v(197) | *Input EMPTY2 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : COREFIFO.v(163) | Input MEMRD is unused. Finished optimization stage 2 on COREFIFO_C1_COREFIFO_C1_0_COREFIFO_Z5 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on DelayFIFOx64_19 ....... Finished optimization stage 2 on DelayFIFOx64_19 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C2 ....... Finished optimization stage 2 on COREFIFO_C2 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_ram_wrapper_64s_64s_6_6_1s_2s_3s ....... @N:CL159 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(42) | Input WCLOCK is unused. @N:CL159 : COREFIFO_C2_COREFIFO_C2_0_ram_wrapper.v(43) | Input RCLOCK is unused. Finished optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_ram_wrapper_64s_64s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_USRAM_top ....... Finished optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_corefifo_sync_scntr_Z4 ....... @N:CL159 : corefifo_sync_scntr.v(97) | Input re_top is unused. @N:CL159 : corefifo_sync_scntr.v(98) | Input empty_top_fwft is unused. Finished optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_corefifo_sync_scntr_Z4 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_COREFIFO_Z3 ....... @W:CL156 : COREFIFO.v(197) | *Input EMPTY2 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : COREFIFO.v(163) | Input MEMRD is unused. Finished optimization stage 2 on COREFIFO_C2_COREFIFO_C2_0_COREFIFO_Z3 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on DelayFIFOx128_18 ....... Finished optimization stage 2 on DelayFIFOx128_18 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C3 ....... Finished optimization stage 2 on COREFIFO_C3 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_ram_wrapper_128s_128s_6_6_1s_2s_3s ....... @N:CL159 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(42) | Input WCLOCK is unused. @N:CL159 : COREFIFO_C3_COREFIFO_C3_0_ram_wrapper.v(43) | Input RCLOCK is unused. Finished optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_ram_wrapper_128s_128s_6_6_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_USRAM_top ....... Finished optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_USRAM_top (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on RAM64x12 ....... Finished optimization stage 2 on RAM64x12 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB) Running optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_corefifo_sync_scntr_Z2 ....... @N:CL159 : corefifo_sync_scntr.v(97) | Input re_top is unused. @N:CL159 : corefifo_sync_scntr.v(98) | Input empty_top_fwft is unused. Finished optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_corefifo_sync_scntr_Z2 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 113MB) Running optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_COREFIFO_Z1 ....... @W:CL156 : COREFIFO.v(197) | *Input EMPTY2 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : COREFIFO.v(163) | Input MEMRD is unused. Finished optimization stage 2 on COREFIFO_C3_COREFIFO_C3_0_COREFIFO_Z1 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 113MB) Running optimization stage 2 on mult192x64 ....... Finished optimization stage 2 on mult192x64 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 113MB) Running optimization stage 2 on mult128x64 ....... Finished optimization stage 2 on mult128x64 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 113MB) Running optimization stage 2 on mult64x64_64s_64s ....... Finished optimization stage 2 on mult64x64_64s_64s (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 113MB) Running optimization stage 2 on mult64x64_64s_65s ....... Finished optimization stage 2 on mult64x64_64s_65s (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 113MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 111MB peak: 113MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime Process completed successfully. # Wed Nov 24 09:50:37 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2021.03M Install: C:\Microsemi\Libero_SoC_v2021.2\SynplifyPro OS: Windows 6.2 Hostname: PLA-LT-C32761 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202103synp1, Build 142R, Built Jun 17 2021 10:57:57, @ @N: : | Running in 64-bit mode File C:\actelprj\RTL\WideMult\WideMult\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Nov 24 09:50:37 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: WideMultTop_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 23MB peak: 24MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime Process completed successfully. # Wed Nov 24 09:50:37 2021 ###########################################################]